1. Technical Field
Various embodiments relate to a semiconductor integrated circuit, and more particularly, to a semiconductor memory apparatus.
2. Related Art
In general, a semiconductor memory apparatus receives a command, an address, data, etc. from an outside, stores the inputted data, and outputs the stored data.
In order to receive a command, an address, data, etc. from an outside, a semiconductor memory apparatus includes a pad for coupling the inside of the semiconductor memory apparatus with the outside.
While the number of pads included in a semiconductor memory apparatus should be increased in order for the semiconductor memory apparatus to store an increased amount of data and perform an increased number of operations, the number of pads which can be included in one semiconductor memory apparatus is limited.
A semiconductor memory apparatus is configured to perform an initializing operation by receiving a reset signal from an outside.
Referring to FIG. 1, a semiconductor memory apparatus includes a reset pad 10, an input buffer 20, and a reset control unit 30.
The reset pad 10 receives an external reset signal RESET_ext from an outside of the semiconductor memory apparatus.
The input buffer 20 receives and buffers the external reset signal RESET_ext of a CML (current mode logic) level and generates an internal reset signal RESET_int of a CMOS (complementary metal oxide semiconductor) level.
The reset control unit 30 is configured to initialize internal circuits (not shown) in response to the internal reset signal RESET_int.
The reset operation of the semiconductor memory apparatus provides advantages in that the initialization and recovered state of the semiconductor memory apparatus are ensured and thus the stability of a system is improved. However, since the reset operation is performed only in limited cases such as the initial power-up stage of the semiconductor memory apparatus and when the initialization of the semiconductor memory apparatus is necessary, the reset pad 10 remains as an unused pad during a normal operation.
Therefore, in order for the semiconductor memory apparatus to store an increased amount of data or perform an increased number of operations, it is necessary to develop a semiconductor memory apparatus capable of efficiently using pads of a limited number.